(1) Field of the Invention
The present invention relates to multilevel interconnects employed in semiconductor technology in general, and in particular, to a method of forming defect free interconnects of high aspect ratio found in quarter-micron technology.
(2) Description of the Related Art
The large, very large and ultra large scale integration of chips, also known as LSI, VLSI and ULSI, respectively, of the semiconductor technology have brought along challenges associated with packing many more devices in smaller spaces. Packing density of chips has been increasing not only in the areal dimensions, but also in the third dimension where many more layers are being added in the vertical direction. Thus, multi-levels of interconnections, or wires, are formed in order to be able to connect the thousands of devices that are formed in the underlying semiconductor substrate. The number of levels of interconnects required for the quarter-micron technology can be upwards of five or more.
Comparing quarter-micron technology with one-micron technology for illustrative purposes, where the feature size refers to the gate length of a metal-oxide semiconductor device, generally all feature sizes are reduced by one quarter on a side. Hence, considering a generalized feature as shown in FIG. 1 having width (x) and thickness (z), the feature has an aspect ratio of (z)/(x). It will be apparent that when the lateral dimensions of the feature are reduced or shrunk, say, by a factor of four, as shown by the phantom lines in FIG. 1, then the width becomes (x/4), and the aspect ratio four times larger. It is with higher aspect ratios that reliability problems arise in forming interconnects in semiconductor substrates. It is proposed in the embodiments of the present invention a method of utilizing a new hard-mask in order to maintain or exceed the required reliability when practicing submicron technologies.
Conventionally, a semiconductor chip contains one or more metal wiring layers that are separated from each other by an insulating layer and are further separated by still another insulating layer from the devices that are formed near the surface of the semiconductor that forms the base of the chip. The wiring stripes are connected to each other and tc the devices at the appropriate places by means of holes that are filled with metal through the insulating layers. The holes that connect the metal lines to each other through the insulating layer are called via holes, while the holes that reach the underlying devices through its insulating layer are called contact holes. Typically, the holes are etched into an insulating layer after the latter has been deposited on the semiconductor substrate on which the chips are fabricated. It is common practice to next blanket deposit metal on the insulating layer thereby filling the holes and then forming the metal lines by etching through a patterned photo resist formed on the metal layer. For the first metal layer, electrical contact is made with the underlying devices through contact holes that allow the metal to descend through the dielectric insulator to the devices. For the second and subsequent wiring layers, the process is repeated and the contact between the metal layers is made through via holes that allow the metal to descend to the lower metal layer(s). It is also common practice to fill the holes separately with metal to form metal plugs first, planarize or smoothen them next with respect to the surface of the insulating layer and then deposit metal layer to make contact with the via plugs and then subtractively etch as before to form the required "personalized" wiring layer.
In forming wiring layers, blanket metal must be patterned. Photolithography is a common approach wherein patterned layers are usually formed by spinning on a layer of phctoresist, projecting light through a photomask with the desired pattern onto the photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist, and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered soluble (positive resist) and be washed away, or insoluble (negative resist) and fix the pattern. In either case, the remaining resist on the surface forms the desired pattern.
Etching of metal lines require precise lithographic processes. The nature of the mask used for etching can affect the lithographic process itself. Thus, when photoresist is used as the mask, its local thickness can vary depending upon the underlying features that it crosses on the substrate. If it crosses a step, for example, then its thickness over the top of the step will be much thinner than that which crosses over low-lying regions. During lithographic exposure, either the thin resist becomes overexposed, or the thicker resist underexposed. Upon development, a resist pattern crossing a step will therefore exhibit a linewidth variation (i.e., narrower on the top of the step). For lines in which step heights approach the size of the linewidth, as would be the case with submicron technologies, such variations in dimension can become unacceptable. It will also be known to those skilled in the art that standing wave effects in thick resist layers reduce lithographic resolution. In addition, reflective substrates also degrade resolution in thick resist films, and for that reason, anti-reflective coating (ARC) is used.
Resolution--which determines the precision of the transferred pattern, say, from a photomask to a photoresist layer to be patterned--is generally governed by the contrast of the resist and also its thickness. In a resist with a perfect contrast, an ideal exposure process would deliver the desired exposing radiation only to the resist region whose dimensions are equal to the pattern of the mask, and there would be no energy delivered elsewhere. In other words, the transferred pattern on the metal would be the exact replica of the pattern in the mask. However, in real exposures, energy is delivered in a more diffused fashion, due to diffraction an scattering. Hence, when developed, the resist will dissolve more in some areas and less in some other areas than required, and the pattern profile will be different from which is copied. It will be appreciated that, under these non-ideal conditions, the thicker the resist, the more sloped or variable will be the walls of the pattern transferred into the resist. This problem, as well as the standing wave and reflections from a reflective surface can be alleviated by employing thin resists, provided that the underlying surface is well planarized. In other words, a thinner mask will in general will yield better resolution.
Photoresist, however, not only consumes time and resources but also endangers contamination from the particulates and etchant solutions. Usually, contamination results from the wet etching used in transferring patterns from the photoresist onto the underlying material. Furthermore, wet etching processes are typically isotropic. Therefore, if the thickness of the film being etched is comparable to the minimum pattern dimensions, undercutting due to isotropic etching becomes intolerable, a problem further exacerbated when using submicron technologies. One alternative pattern transfer method that offers the capability of non-isotropic etching is dry etching, as is well known. In dry etching, a hard-mask, such as silicon dioxide or silicon nitride is used in place of photoresist. The etching process is made to be as highly selective as possible against etching the mask layer material, and against the material under the film that is being etched.
In prior art, methods have been devised to employ hard-masks in forming multilayer interconnects in semiconductors to prevent formation of defects as described Shen, et al., in U.S. Pat. No. 5,665,641. Shen points out that the need to have hard masks for metal etching has become critical for the semiconductor industry. The need is driven by the depth of field requirement of the lithography process which is provided by using thinner photoresist. However, thinner resists cause metal etching problems, because the metal etch chemistry exhibits poor selectivity to the resist. This, in turn, causes difficulties in control of critical dimensions (CD). Accordingly, Shen proposes a process for forming a hard mask over an aluminum-containing layer for patterning and etching the aluminum-containing layer to define interconnects. The hard mask must be deposited at a lower temperature than the deposition temperature of the interconnect metal so that the formation of defects in the metal lines is prevented.
Shen's method is shown in FIG. 2. A metal layer (10) comprising an aluminum-containing alloy is formed over an oxide layer (12). The oxide layer (12) is in turn supported over a silicon substrate (not shown). An optional barrier layer (14) of titanium/titanium nitride provides controlled crystallization the Al alloy and may be interposed between the oxide layer (12) and the interconnect layer (10). In patterning the aluminum-containing interconnect layer (10), an anti-reflection coating (ARC) (16) is first deposited on the interconnect layer, followed by formation of the hard mask (18) thereon, which may comprise silicon dioxide or silicon nitride. A photoresist layer (not shown) is deposited on the hard mask (18) and is subsequently exposed to electromagnetic radiation of the appropriate wavelength and developed. Depending upon the nature of the resist (positive or negative), the developed or undeveloped portions are removed, thereby exposing portions of the surface of the underlying oxide (18). Next, exposed portions are removed by etching to expose corresponding portions of the surface of the ARC (16), which in turn are also removed by etching. The process is repeated to expose corresponding portion of the surface of the interconnect layer (10), which are then removed by etching to form the desired interconnect pattern.
Baker, et al., in U.S. Pat. No. 5,567,334 proposes a method for creating digital micromirror device using an aluminum hard mask. In this manner, he avoids the use of a sacrificial oxide hard mask. Cote, et al., on the other hand, use a hard metal in forming electrically conducting vias and lines by a three step process. As described in U.S. Pat. No. 5,262,354, first, a controlled amount of soft, low resistivity metal is deposited in a trench or hole to a point below the top surface of a dielectric layer in which the trench or hole is formed. Subsequently, the low resistivity metal is overcoated with a hard metal such CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure.
Lee, in U.S. Pat. No. 5,431,770 shows a method for forming transistors having sublithograpic features, for example, gates. A patterned hard-mask (formed, for example from PETEOS) is created overlying oxide and polysilicon layers. The dimensions of the hard-mask are reduced by isotropic etching. The reduced dimension hard-mask is used with an anisotropic etching process to define a reduced dimension feature such as a gate.
It will be apparent to those skilled in the art that in prior art methods, there is usually a trade-off between having a thin enough mask to provide the required resolution for submicron technology features on the one hand, and making the mask thick enough, on the other, so that the potential for damaging the metal line is minimized. What is needed is a thin hard-mask of appropriate material that can be used directly over the metal to be etched and not be affected by the etchant gases so as to cause any defects in the underlying metal to be etched. This is shown in the embodiments of the present invention.